Today's integrated circuits (ICs) include a vast number of transistor devices formed in a semiconductor and currently, smaller devices are the key trend to enhance device performance and to increase reliability. As devices are scaled down, however, the integration technology becomes more complex and new methods are needed to maintain the expected performance enhancement from one generation of devices to the next. In this regard, the semiconductor that has progressed the farthest is the primary semiconductor material of microelectronics, silicon (Si), or more broadly, Si-based materials. One such Si-based material of high importance for microelectronics is a silicon germanium (SiGe) alloy.
One of the most important indicators of potential device performance is the carrier mobility, and as the scaling trend continues there is a great difficulty in keeping the carrier mobility high in these scaled devices of the deep submicron generations. A promising avenue towards better carrier mobility is to slightly modify the semiconductor that serves as the raw material for device fabrication. It has been known, and recently studied, that tensilely or compressively strained semiconductors have intriguing carrier properties. In particular, a 90-95% improvement in the electron mobility has been achieved in a strained silicon (Si) channel nMOS as described in U.S. Pat. No. 6,649,492 B2 to J. O. Chu et al. entitled “A strained Si Based Layer Made by UHV-CVD, and Devices Therein” incorporated herein by reference.
Similarly for hole enhancement, compressively-strained buried germanium (Ge) MODFETs have yielded high hole mobilities as described by S. J. Koester et al. in “Extremely high transconductance Ge/Si0.4Ge0.6 p-MODFETs grown by UHV-CVD,” IEEE Elect. Dev. Lett. 21, 110 (2000), and in PCT Patent Application No. US 00/06258, filed Mar. 11, 2000 (Publication No. WO 00/54338) entitled “A High Speed Ge-Channel SiGe/Ge/SiGe Heterostructure for Field Effect Transistor” by J. O. Chu, and more recently, in U.S. Ser. No. 10/876,155, filed Jun. 24, 2004 and entitled “Integration of Strained Ge into Advanced CMOS Technology” by H. Shang et al., all incorporated herein by reference.
Finally, the synergistic combination of tensilely and compressively strained SiGe regions within the same wafer is also described in U.S. Pat. No. 6,963,078, to J. O. Chu, entitled “Dual Strain-State SiGe Layer for Microelectronics.” This disclosure is also incorporated herein by reference.
Ideally, for high performance integrated circuits one would like to have the electron conduction type devices, such as nMOS, nMODFET to be hosted in a tensilely strained Si or SiGe material, while the hole conduction type devices such as pMOS, pMODFET be hosted in a compressively strained Ge or SiGe material. Furthermore, it is well known to those skilled in the art that in a strained silicon channel the degree of electron nobility enhancement strongly depends on the strain level in the strain silicon or silicon carbon (SiC) alloy layer. In other words, the higher the imposed “tensile” strain, the higher the induced enhancement on electron mobility would be. The most common practice for applying or inducing tensile strain to a silicon or SiC layer is through the use of an underlying silicon germanium (SiGe) buffer layer, which is typically a relaxed SiGe layer having a larger lattice constant as compared to bulk silicon. Hence, by increasing the Ge content of the underlying SiGe buffer layer, which in turn increases the lattice constant of the SiGe buffer layer, a higher “tensile” strain can be imposed to the silicon or SiC layer due to a larger lattice mismatch between the two layers.
It is also well known that metal oxide semiconductor field effect transistor (MOSFET) devices fabricated on silicon-on-insulator (SOI) substrates can have up to 25-35% better performance than those built on bulk Si wafers due to lower parasitic capacitance of the source/drain junction, reduced short channel effects and better device isolation. This is reported, for example, by G. G. Shahidi, “SOI Technology for GHz Era”, IBM J. Res. & Dev., Vol. 46, pp. 121-131 (2002). Thus, it is desirable to combine these two effects to generate a strained silicon or SiC channel having enhanced carrier mobility on a SiGe-on-insulator (SGOI) substrate to achieve an even higher device performance gain.
In view of the above, a method is needed to generate a high Ge content (x>30%), near defect-free SGOI substrate suitable for high mobility strained-Si or strained-SiC nFET devices.
Previously, the ability to create a near defect-free SGOI substrate with a high Ge content (x>30%) has been a difficult problem to address. Although thermally-mixed (TM) SGOI as described in U.S. Pat. No. 6,805,962 B2 to S. W. Bedell et al. entitled “Method of Creating High Quality Relaxed SiGe-On-Insulator for Strained Si CMOS Applications” incorporated herein by reference, has provided an alternative approach to creating a SGOI substrate, the SiGe layers typically formed on the TM-SGOI wafers is only partially relaxed, i.e., about 50 to 80% and have yet to achieve a fully relaxed SiGe layer having greater than 90% degree of relaxation.
In a similar fashion, the same difficulty has been encountered in preparation of SGOI substrates generated by the alternate SIMOX approach. See, for example, T. Mizuno et al., “High Performance Strained-Si p-MOSFETs on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology”, IEDM Tech. Dig., pp. 934-936 (1999).
Recently, it has been demonstrated that a fully relaxed (>90%) SiGe buffer layer can be transferred to a handle wafer through a wafer bonding technique which is further described in U.S. Pat. No. 6,524,935 to D. F. Canaperi et al. However, the bonded SGOI wafers prepared from this prior art process still suffer from various bonding related defects, such as blisters, bubbles, voids, etc., especially for high Ge content SGOI wafers where the Ge content is larger than 25 atomic (at.) %.
U.S. Patent Application Publication No. 2006/0054891 to Chu et al. discloses a method of preparing a substantially defect free SGOI substrate including a SiGe layer having a Ge content of greater than 25%. The method disclosed in the '891 publication is similar to the present invention except that the implant step uses only hydrogen ions. The method disclosed in the '891 publication is basically restricted to a “relatively” high temperature H2+ splitting process which is from about 450° to about 650° C.
In view of the prior art mentioned above, a new and improved method of fabricating a substantially defect free strained semiconductor-on-insulator substrate is needed.